a. Field of the Invention
The present invention generally relates to integrated circuits. More specifically, this invention relates to scan flip flop architecture used in test and functional modes of operation.
b. Description of the Related Art
There exists an ever increasing demand for faster and more complex integrated circuits (IC). Further, ICs today incorporate large numbers of scan flip flop circuitry. Testing of ICs, both combinational and sequential logic after fabrication is a crucial step in the manufacturing process to ensure performance and reliability.
A synchronous scan flip flop 360 includes a data input 368, a reset input 370, a serial input 372, a scan enable input 374, a clock input 376, and a device output 378. In addition, the synchronous scan flip flop 360 includes an inverter 384, a logic gate 362, a multiplexer 364, and a storage element 366. The inverter 384 changes an input's logic state from logic 0 to logic 1 or from logic 1 to logic 0. The logic gate 362 receives a signal from the data input 368 and the reset input 370. The data input 368 and reset input 370 are used during functional mode. The multiplexer 364 receives the first output 380 from the logic gate 362, the serial input 372, and the scan enable input 374. The serial input 372 is used to input a serial input sequence during test mode or scan shift mode of operation. Therefore, the multiplexer 364, according to the scan enable input 374, will select either a functional mode input sequence (output of the AND gate) or a serial input sequence. The storage element 366 receives the second output 382 from the multiplexer 364 and a clock signal 376. The storage element 366 will transmit the second output 382 of the multiplexer 366 to the device output 378 upon a rising edge or a falling edge of the clock signal 376 depending on the active edge of clock.
In functional mode the scan enable input 374 is de-asserted and has a logic 0 state causing the multiplexer 364 to select the first output 380 of the logic gate 362. Under functional non-reset operation the reset input 370 will have a logic 0 state and the first output 380 of the AND gate 364 will be equal to the data input 368 irrespective of the logic state of the serial input 372. Thus, the device output 378 will be equal to the data input 368. To reset the synchronous scan flip flop 360, the reset input 370 is asserted or has a logic 1 state. The inverter 384 converts the logic 1 state from the reset input 370 to a logic 0 state causing the first output 380 of the logic gate 362 to have a logic 0 state. Therefore, whenever the reset input 370 is asserted in functional mode the device output 378 will have a logic 0 state. The synchronous scan flip flop 360 can only be reset in functional mode.
Test mode generally refers to global testing of the IC in which the synchronous scan flip flop 360 is included. Included in test mode is scan mode where the combinational and sequential circuits are tested. Both test mode and scan mode permit manufactures to test the integrity of the final assembly. Testing of scan flip flop includes selecting test mode, providing testing inputs, and finally comparing the serial input sequence response with an expected output. In test mode, the serial input sequence is provided at the serial input 372. Upon assertion of a global testing sequence the scan enable input 374 is asserted, or has a logic state, causing the second output 382 of the multiplexer 364 to be equal to the serial input 372. Therefore, the device output 378 is equal to the serial input 372 or the serial input sequence.
The inventors have recognized advantages by eliminating the inverter 384. One being a reduction in the scan flip flop area. Reducing the size of the scan flip flop allows for a substantial reduction in the overall size of an IC including several scan flip flops. Another advantage recognized by the invertors is a reduction in logic gate delay on the data path in turn improving data transfer rates while operating in functional mode.